1. Field of the Invention
The present invention relates to a voltage adjusting circuit, and in particular to a voltage adjusting circuit that can output a stable output voltage regardless of a temperature variation.
2. Description of the Background Art
In general, a high voltage must be applied to a drain of a memory cell in a program or erase operation of a flash memory. The high voltage is generated by using an external power source. To reduce unnecessary power consumption, a voltage adjusting circuit for constantly maintaining the high voltage regardless of the external power source is required.
Referring to FIG. 1, a conventional voltage adjusting circuit includes a reference voltage generator 10, a differential amplifier 12 and a voltage divider 14.
The voltage divider 14 has an NMOS transistor 31 connected in series between a power supply voltage Vcc and a ground voltage Vss, and resisters R1, R2 that are passive elements. A gate of the NMOS transistor 31 is connected to an output terminal of the differential amplifier 12, and a noninverted input terminal (+) and an inverted input terminal (-) of the differential amplifier 12 are connected respectively to a common node 50 of the resisters R1, R2 and an output terminal of the reference voltage generator 10.
The operation of the conventional voltage adjusting circuit will now be described.
The reference voltage generator 10 generates a reference voltage Vref from the external voltage Vcc. Thereafter, the reference voltage Vref is compared in the differential amplifier 12 with a divided voltage Vreg from the voltage divider 14. As a result, a turn-on degree of the NMOS transistor 31 is controlled by a comparison voltage Vdiff outputted from the differential amplifier 12, thus varying an output voltage Vout. In this case, the output voltage Vout is represented by the following expression. EQU Vout-Vref.times.(1+R1/R2)
However, when the output voltage Vout is varied, the divided voltage Vreg is also varied by the resisters R1, R2. Therefore, the differential amplifier 12 controls the turn-on degree of the NMOS transistor 31 by comparing the reference voltage Vref with the varied distribution voltage Vreg. Accordingly, the conventional voltage adjusting circuit generates a final output voltage Vout by repeatedly performing the above operation until the levels of the reference voltage Vref and the distribution voltage Vreg are identical.
In general, a program or erase operation of a flash EEPROM cell, a lock-out level decision, a high voltage pumping, a negative voltage pumping and the like are more exactly and stably carried out when a voltage to be applied is influenced by a variation in temperature as less as possible. However, the conventional voltage adjusting circuit providing a voltage for performing the above-mentioned operations has a predetermined error according to a temperature variation.
That is, when a temperature is varied in the conventional voltage adjusting circuit, the reference voltage Vref outputted from the reference voltage generator is also varied. For example, the reference voltage Vref of a bandgap reference voltage generator has a variation rate of approximately 3%. The output voltage Vout has a predetermined error according to a temperature variation because the output voltage Vout is varied as much as the variation rate of the reference voltage Vref.